Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

First 7 nm EUV Chip Tapes Out at TSMC

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC’s second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML’s Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

While the advantages of N7+ over its predecessors are not significant (e.g., TSMC has never mentioned performance increases that the new tech is expected to bring), it will still almost certainly be embraced wholeheartedly by developers of mobile SoCs who need to release new chips every year. That said, it is not surprising that TSMC has already taped out the first chip using its N7+ technology. Furthermore, the company is prepping a specialized version of N7 process aimed at the automotive industry, which indicates that N7/N7+ is going to be a “long” node.

TSMC is not disclosing the name of the customer whose N7+ SoC it has taped out, but considering the foundry’s alpha customers for new process technologies in the recent years, the leading suspects are obvious.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10% 20%
Performance 40% 20% 30% ? same (?) 15%
Area Reduction none >50% 70% >37% ~17% 45%

5 nm on Track

After N7+ comes TSMC’s first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC’s N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

EDA tools for the N5 node will be ready in November, so chip designs may be well underway now. But while many foundation IP blocks for N5 are ready today, there are important missing pieces, such as PCIe Gen 4 and USB 3.1 PHYs, which may not be ready until June. For some of TSMC's clients the lack of these pieces is not a problem, but many will have to wait.

One of the factors that prevents smaller companies from designing FinFET chips is development cost. Some estimates put the average cost to develop an SoC at around $150 million in labor and IP licenses. With N5 generation, these expenditures will rise to $200 – $250 million, according to EETAsia, which will limit the number of parties interested in using the tech.

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Source: EETAsia

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  • stanleyipkiss - Tuesday, October 9, 2018 - link

    If TSMC can be at 5nm before Intel gets to 10nm (which is equivalent sort of to TSMC 7nm) does that mean that Intel has REALLY lost process node advantage for the first time in 20+ years?
  • shabby - Tuesday, October 9, 2018 - link

    Looks like, they made a bet and lost.
  • Sahrin - Tuesday, October 9, 2018 - link

    I don't think it's that so much as the company completely lost focus after the Haswell/Broadwell generation.

    They spent $17B acquiring which is effectively completely wasted in this era of customer foundry order ASIC's. They released Optane which so far as I can tell is making exactly zero progress in the market while eating up fab capacity.

    The company really seems to be in chaos, which is bizarre for an organization that was the gold standard since basically Fairchild.
  • sharath.naik - Wednesday, October 10, 2018 - link

    I don't believe Intel has lost its edge. I think this is more to do with business people making a decision to not move to 10nm because there is no competition. This allows them to still make their products in 14nm avoiding research cost and make huge profits until the competition catches up. This is terrible for technology but good for Intel's bank accounts
  • psychobriggsy - Wednesday, October 10, 2018 - link

    Absolutely not. Intel is a very paranoid business, operationally. They know that part of their leadership comes from having the leading edge nodes.

    The fact is that they do not have enough 14nm capacity to satisfy the market demand now, due to not having migrated core products to 10nm already. 10nm is being redesigned to be slightly less dense but working, but it won't be ready until next year, potentially late in the year (or worse).

    Intel will still make big profits for now due to also having good designs, but they have lost the manufacturing lead.
  • FreckledTrout - Wednesday, October 10, 2018 - link

    As far as I understand Intel is moving to use EUV for there 10nm node which likely won't reduce density like you stated. I suspect Intel's 10nm will land density wise somewhere between TSMC's 5nm and 7nm so really they aren't behind by much but they certainly are no longer leading.
  • ajc9988 - Wednesday, October 10, 2018 - link

    I think you missed the memo. End of August or beginning of September, Intel ceded EUV to TSMC and Samsung fabs, saying they will not introduce EUV until 2021, which roughly coincides with Intel's 7nm time frame. The 10nm, before the gutting and making less dense, would have been only a couple percent over the theoretical density of TSMC. Meanwhile, TSMC put out Apple's 7nm chip, meaning they have the lead. Intel's 14nm++ is NOT more dense than 7nm at TSMC. So, in absolute terms, Intel is not the leading process, and some argue it has not been since the introduction of a TSMC 10nm production, with Intel's 14nm being comparable to other fab's 10nm, generally. Meanwhile, Intel's 10nm won't have products to market on the node until 2H 2019.
  • FreckledTrout - Thursday, October 11, 2018 - link

    I did miss that memo :)
  • Wilco1 - Wednesday, October 10, 2018 - link

    Intel's 10nm doesn't use EUV and will have worse density than TSMC 7nm. Originally it would be about the same density, but the feature sizes have been relaxed to get it working. This is like the 14+ and 14++ processes which also have worse density than the original 14nm process.
  • sing_electric - Thursday, October 11, 2018 - link

    While it might be true that Intel's 10nm is better than TSMC's 1st 7nm (which I doubt somewhat - I think they're probably roughly comparable in density), the fact of the matter is that Intel was shipping 14nm processors in bulk when TSMC was doing 20nm, and Intel had planned to be at 10nm before TSMC was doing any 7nm.

    At this point, TSMC will be on its 2nd gen 7nm before Intel's 10nm moves past a few niche processors.

    I don't think Intel is BEHIND in manufacturing by that much, but they're certainly stumbling, and they've lost all, or most of their lead.

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