OK, Intel, I'm freakin' sick of the Lake codenames and the fact that so many being with C. How the hell are your customers supposed to keep track of this???
Agreed so much! Furthermore, if Ice Lake really is a new core design, it would be helpful to more readily identify the difference from Skylake by using a different geographic feature.
Not only, server parts are lower clocked than desktop ones, so no matter if 10nm or 10nm+ or 10nm++, expecialy if the core count is high the peak clock speed is not so relevant. If a customer want fast clocks it can chose one of the present Xeon 14nm parts with a medium/low core count.
"For Ice Lake-U, Intel has stated that the CPU, which is being built on their second-generation 10nm "10+" process, will be paired with a new generation ‘14nm class’ chipset."
That is from Anandtech, not Intel and they are wrong. Have a look at the last slide from that page you linked. It clearly shows 10nm+ debuting in 2020.
Keep in mind this article is for only IceLake versions of Xeons, Ice Lake mobile chips like new Dell XPS 15 2in1 are available this year.
It sounds like the planned is for an upgrade path for 56 core to Ice Lake compatible mother boards - which looks like Intel has at least 56 core planned for 10nm Ice Lake.
On 10nm vs 10+, it probably assume original Intel 10nm Cannon Lake is just trial run and Ice Lkae is main stream.
This is actually good news - one concern I had before is that Ice Lake was only limited to U/Y chips and it appears not so.
Apparently they have done a renaming, thinking at a 10nm+++, so actual cadence is 10nm(10nm+), 10nm+(10nm++), 10nm++(10nm+++). The old plain 10nm is died or changed or fixed.
Code names (such as all the lake names) are specifically used by companies to obscure details from competitors. It seems like the code names are doing exactly what they intended to do. Marketing is calling their chips the ___ generation. That doesn't seem too difficult to tell that 7th generation is newer than 3rd generation.
actually the only thing that was 10nm was the original cannonlake if i recall correctly. so all those icelake laptop cpus that are coming out right now are all on 10nm+. server cpus may be different but i think intel have given up on regular 10nm. the density on 10nm was 100 megatransistors per mm2 and 10nm+ is around 60 i think.
just like 14nm was about 45 and 14nm+ was more in the high 30's. making the gates a bit bigger helps with clocks etc but also means you lose some density. but it makes a much more useable process.
Cannonlake 10nm was a clusterfuck and they basically had to start from the beginning, so Icelake is on 10nm, but it's effectively a different node. On the official Intel slide it clearly shows 10nm+ in 2020. Icelake debutes in 2019.
We are still in middle of Q3, so it still possible that it be launch Q3, It sounds like Intel is making refinements - because original Dell mailing has new XPS 13 2in1 coming in July.
Not sure it matters what + it means - but Ice Lake's 10nm is new revised version of failed 10nm Cannon Lake. So I not sure it consider 10nm or 10nm+, but instead 10nm take 2/ as for the timing it actually not end of 2020 but in 2020 framed. Technically we are not that far away now, we are in 2nd half of 2019 and Ice Lake mobiles should be out in this quarter and my guess higher core versions and clock speed version in 1st half of 2020 follow by Xeon's in 2nd half.
But the key is Intel is over or shortly over with Skylake version and all the backlash with Spectre/Meltodon stuff which I have yes send some real virus using it.
No, it's not. That Intel slide you saw is "temporally arbitrary", since Intel would prefer to not highlight that their original 10nm node was basically a mere beta node. In December 2017 they "released" (in very low volume) a barely functional Cannon Lake dual core i3 CPU fabbed on that node, with a disabled iGPU, horrible clocks and thermals, and targeted exclusively at Chinese schools.
Why? In order to report a nominal 2017 release of CPUs fabbed on their 10nm node to their shareholders, hoping at least the gullible ones will buy it. There was no other reason for that "release", since Cannon Lake / 1st gen 10nm node's yields were truly *atrocious* (apparently Ice Lake / 2nd gen 10nm+'s yields are "barely tolerable", but Intel can no longer afford to delay the launch of Ice Lake).
Ice Lake is to be released on their 2nd gen 10nm+ node, while Tiger Lake will be released on their 3rd gen 10nm++ node. They avoid explicitly calling Ice Lake's node "second gen" though, because they don't want to remind people of Canned Lake. Due to Intel's still poor yields Ice Lake U/Y will be co-released with Comet Lake U/Y, and based on leaks there will be no mid power (-H) and full power (-S) version of Ice Lake. It's still unknown if Intel will manage to release Ice Lake Xeon with acceptable yields (and thus acceptable profit). Cooper Lake's job is to buy time for Intel to fix their continuing 10nm+ issues.
Gotta give credit to all you folks publishing articles - how do you not get drowned in the Lakes already !? Please make it easy for everyone Intel ! OTOH, will be good to see this go up against Rome HCC server part. TDP?
having trouble getting exclusive sneak peeks from Intel's competitor? sad.
At least take the time to list the TDP of the parts advertised on this page rather than selectively showing information about parts which *may* get released 14 months from now.
Don't see how these will be competitive with 64C ROME likely offering more performance at lower power use, or the same performance at half the wattage. The only advantage these parts will have, is in heavy AVX512 workloads where they will likely beat the ROME CPUs due to higher through-put per core (wider SIMD pipes). Other than that, essentially DOA.
Of course the GPU wins by a big margin in other software. You need to know what you are going to do and use the appropriate hardware for it. Computer simulations tend to run poorly on GPUs, but can benefit greatly by AVX 512: https://www.simutechgroup.com/images/easyblog_arti...
16 memory channels for the socketed 56-core version? Don't hold your breath for that. I think they will only export 8 of the channels to the socket, for various reasons. First, the current Xeon Platinum 9200 series have a BGA with 5903 contacts, significantly more than the 4189 pins which I would expect LGA4189 to have. And only part of the pin increase compared to the Skylake/Cascade Lake LGA3647 socket can be used for the extra memory channels as I would expect power draw to go up also (especially if you want to feed those 56 cores at a reasonable clock speed). And I would guess they may want to export some more PCIe channels also to compete with the higher number of channels supported by AMD? So there is no way you can also pass 16 memory channels through that socket. Moreover, if the 2 die-on-socket Cooper Lake would have more memory channels on the same socket as the single die Cooper Lake or Ice Lake, you'd still need different motherboards. So what would be the point of that exercise? You could then go as well with a socket with even more pins to better satisfy the power needs of a 2 die Cooper Lake socket.
Intel could be reverting back to a serial memory interface that would require an additional buffer chip on the motherboard to fan out to normal DIMM modules. Most of those implementations have traditionally permitted a doubling of channel count vs. parallel solutions at the time. However, such a schema would not be compatible with currently planned boards.
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lefty2 - Tuesday, August 6, 2019 - link
I think you are mistaken. Ice lake is on 10nm, not 10nm+. It even says that on official Intel slides. 10nm+ won't appear until end of 2020.ken.c - Tuesday, August 6, 2019 - link
OK, Intel, I'm freakin' sick of the Lake codenames and the fact that so many being with C. How the hell are your customers supposed to keep track of this???ken.c - Tuesday, August 6, 2019 - link
oops, that wasn't meant as a reply to lefty2, sorry 'bout that.PeachNCream - Tuesday, August 6, 2019 - link
Agreed so much! Furthermore, if Ice Lake really is a new core design, it would be helpful to more readily identify the difference from Skylake by using a different geographic feature.rocky12345 - Tuesday, August 6, 2019 - link
That and a new socket almost every time they dream up something new.rocky12345 - Tuesday, August 6, 2019 - link
Just wanted to add I was more referring to the desktop sector.JohanAnandtech - Tuesday, August 6, 2019 - link
You have my vote too. My brains refuse to accept another "Lake" when it is a different design :-)Phynaz - Tuesday, August 6, 2019 - link
They’re code names. Who cares?Gondalf - Wednesday, August 7, 2019 - link
Not only, server parts are lower clocked than desktop ones, so no matter if 10nm or 10nm+ or 10nm++, expecialy if the core count is high the peak clock speed is not so relevant. If a customer want fast clocks it can chose one of the present Xeon 14nm parts with a medium/low core count.James5mith - Tuesday, August 6, 2019 - link
From the Deep dive last week:"For Ice Lake-U, Intel has stated that the CPU, which is being built on their second-generation 10nm "10+" process, will be paired with a new generation ‘14nm class’ chipset."
https://www.anandtech.com/show/14514/examining-int...
lefty2 - Tuesday, August 6, 2019 - link
That is from Anandtech, not Intel and they are wrong. Have a look at the last slide from that page you linked. It clearly shows 10nm+ debuting in 2020.cheshirster - Tuesday, August 6, 2019 - link
"It clearly shows 10nm+ debuting in 2020."And where can i buy Ice Lake in 2019?
HStewart - Tuesday, August 6, 2019 - link
Keep in mind this article is for only IceLake versions of Xeons, Ice Lake mobile chips like new Dell XPS 15 2in1 are available this year.It sounds like the planned is for an upgrade path for 56 core to Ice Lake compatible mother boards - which looks like Intel has at least 56 core planned for 10nm Ice Lake.
On 10nm vs 10+, it probably assume original Intel 10nm Cannon Lake is just trial run and Ice Lkae is main stream.
This is actually good news - one concern I had before is that Ice Lake was only limited to U/Y chips and it appears not so.
Gondalf - Wednesday, August 7, 2019 - link
Apparently they have done a renaming, thinking at a 10nm+++, so actual cadence is 10nm(10nm+), 10nm+(10nm++), 10nm++(10nm+++). The old plain 10nm is died or changed or fixed.tamalero - Sunday, August 11, 2019 - link
Lol, so they gave up and they are using now "glue" ? XDEris_Floralia - Tuesday, August 6, 2019 - link
Another victim of Intel's 10nm marketing mess.dullard - Tuesday, August 6, 2019 - link
Code names (such as all the lake names) are specifically used by companies to obscure details from competitors. It seems like the code names are doing exactly what they intended to do. Marketing is calling their chips the ___ generation. That doesn't seem too difficult to tell that 7th generation is newer than 3rd generation.bobhumplick - Tuesday, August 6, 2019 - link
actually the only thing that was 10nm was the original cannonlake if i recall correctly. so all those icelake laptop cpus that are coming out right now are all on 10nm+. server cpus may be different but i think intel have given up on regular 10nm. the density on 10nm was 100 megatransistors per mm2 and 10nm+ is around 60 i think.just like 14nm was about 45 and 14nm+ was more in the high 30's. making the gates a bit bigger helps with clocks etc but also means you lose some density. but it makes a much more useable process.
lefty2 - Tuesday, August 6, 2019 - link
Cannonlake 10nm was a clusterfuck and they basically had to start from the beginning, so Icelake is on 10nm, but it's effectively a different node. On the official Intel slide it clearly shows 10nm+ in 2020. Icelake debutes in 2019.cheshirster - Tuesday, August 6, 2019 - link
"Icelake debutes in 2019"Icelake paperlaunched in 2019
lefty2 - Tuesday, August 6, 2019 - link
Paper launched in summer 2019. Actual launch in Q4 2019HStewart - Tuesday, August 6, 2019 - link
We are still in middle of Q3, so it still possible that it be launch Q3, It sounds like Intel is making refinements - because original Dell mailing has new XPS 13 2in1 coming in July.HStewart - Tuesday, August 6, 2019 - link
Not sure it matters what + it means - but Ice Lake's 10nm is new revised version of failed 10nm Cannon Lake. So I not sure it consider 10nm or 10nm+, but instead 10nm take 2/ as for the timing it actually not end of 2020 but in 2020 framed. Technically we are not that far away now, we are in 2nd half of 2019 and Ice Lake mobiles should be out in this quarter and my guess higher core versions and clock speed version in 1st half of 2020 follow by Xeon's in 2nd half.But the key is Intel is over or shortly over with Skylake version and all the backlash with Spectre/Meltodon stuff which I have yes send some real virus using it.
Santoval - Thursday, August 8, 2019 - link
No, it's not. That Intel slide you saw is "temporally arbitrary", since Intel would prefer to not highlight that their original 10nm node was basically a mere beta node. In December 2017 they "released" (in very low volume) a barely functional Cannon Lake dual core i3 CPU fabbed on that node, with a disabled iGPU, horrible clocks and thermals, and targeted exclusively at Chinese schools.Why? In order to report a nominal 2017 release of CPUs fabbed on their 10nm node to their shareholders, hoping at least the gullible ones will buy it. There was no other reason for that "release", since Cannon Lake / 1st gen 10nm node's yields were truly *atrocious* (apparently Ice Lake / 2nd gen 10nm+'s yields are "barely tolerable", but Intel can no longer afford to delay the launch of Ice Lake).
Ice Lake is to be released on their 2nd gen 10nm+ node, while Tiger Lake will be released on their 3rd gen 10nm++ node. They avoid explicitly calling Ice Lake's node "second gen" though, because they don't want to remind people of Canned Lake. Due to Intel's still poor yields Ice Lake U/Y will be co-released with Comet Lake U/Y, and based on leaks there will be no mid power (-H) and full power (-S) version of Ice Lake. It's still unknown if Intel will manage to release Ice Lake Xeon with acceptable yields (and thus acceptable profit). Cooper Lake's job is to buy time for Intel to fix their continuing 10nm+ issues.
Teckk - Tuesday, August 6, 2019 - link
Gotta give credit to all you folks publishing articles - how do you not get drowned in the Lakes already !?Please make it easy for everyone Intel !
OTOH, will be good to see this go up against Rome HCC server part. TDP?
liquidaim - Tuesday, August 6, 2019 - link
having trouble getting exclusive sneak peeks from Intel's competitor? sad.At least take the time to list the TDP of the parts advertised on this page rather than selectively showing information about parts which *may* get released 14 months from now.
AshlayW - Tuesday, August 6, 2019 - link
Don't see how these will be competitive with 64C ROME likely offering more performance at lower power use, or the same performance at half the wattage. The only advantage these parts will have, is in heavy AVX512 workloads where they will likely beat the ROME CPUs due to higher through-put per core (wider SIMD pipes). Other than that, essentially DOA.quorm - Tuesday, August 6, 2019 - link
Is there any workload that runs better on AVX512 than a gpu?dullard - Tuesday, August 6, 2019 - link
Yes. Financial simulations for example (see the MC Libor Swaption Portfolio): https://www.xcelerit.com/computing-benchmarks/insi...Of course the GPU wins by a big margin in other software. You need to know what you are going to do and use the appropriate hardware for it. Computer simulations tend to run poorly on GPUs, but can benefit greatly by AVX 512: https://www.simutechgroup.com/images/easyblog_arti...
HollyDOL - Wednesday, August 7, 2019 - link
Huh, Adapter with this pin count sounds a bit scary... and expensiveKurtL - Wednesday, August 7, 2019 - link
16 memory channels for the socketed 56-core version? Don't hold your breath for that. I think they will only export 8 of the channels to the socket, for various reasons. First, the current Xeon Platinum 9200 series have a BGA with 5903 contacts, significantly more than the 4189 pins which I would expect LGA4189 to have. And only part of the pin increase compared to the Skylake/Cascade Lake LGA3647 socket can be used for the extra memory channels as I would expect power draw to go up also (especially if you want to feed those 56 cores at a reasonable clock speed). And I would guess they may want to export some more PCIe channels also to compete with the higher number of channels supported by AMD? So there is no way you can also pass 16 memory channels through that socket. Moreover, if the 2 die-on-socket Cooper Lake would have more memory channels on the same socket as the single die Cooper Lake or Ice Lake, you'd still need different motherboards. So what would be the point of that exercise? You could then go as well with a socket with even more pins to better satisfy the power needs of a 2 die Cooper Lake socket.Kevin G - Wednesday, August 7, 2019 - link
Intel could be reverting back to a serial memory interface that would require an additional buffer chip on the motherboard to fan out to normal DIMM modules. Most of those implementations have traditionally permitted a doubling of channel count vs. parallel solutions at the time. However, such a schema would not be compatible with currently planned boards.